Position: Design Verification Engineer
Department: Project dept.
- Objectives.
- Work and support to Project department
- Main Responsibilities
- IP/SOC design verification
- Review the IP/SOC specification and architecture
- Extract the features and define the verification plan
- Execute the verification plan through testbench development, test generation, failure analysis, and coverage analysis/closure.
- RTL and gate level simulation
- Design verification methodology and flow implementation and improvement
- Other tasks as required from the Manager/ BOD.
- Requirements & Qualification.
- Good command in office software (Word, Excel, PowerPoint, )
- Good understanding of computer architecture and Verilog
- 3+ years of experience in related work (IP/SOC design verification)
- Working experience of UPF-based power-aware simulation
- Working experience of System Verilog Assertion (SVA)
- Working experience of scripts in languages such as Perl and/or Python
- Sophisticated knowledge of standard SoC design and verification flows including RTL design, simulation and testbench development, coverage analysis and constrained random testing
- Advanced Knowledge of UVM
- Facilitating collaboration within and across teams to root-cause and debug issues
- Good decision-making skill respecting team members opinions
- Good communication skill to collaborate with HW/SW development teams with customers
- Ability to work independently or as an active member of a team.
- Finishing tasks from Project dept/ BOD
- Benifits
- 12 days of annual leave.
- Annual health check.
- Annual review salary.
- Annual company trip.
- Performance bonus depends on company performance.
- Training benefits and Development.
- Insurance.
- Introduction to the company
The company was launched with the vision of Leading advanced technology with system semiconductors mainly targeting AI driving SOC, Mega MCU, and Gateway SOC for the computation and network domain. We aim to provide world top solutions that includes the design of semiconductors and software. The initial funding to move forward is already secured and additional follow-up funding is scheduled. All current members are from well-known global big semiconductor companies. HQ is in Singapore, and we are setting up an engineering R&D center in Vietnam to develop semiconductor, IC design and firmware for the AI SOCs.