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Responsibilities
Define DFT specification, finalize DFT Strategy to achieve the testing target.
Perform Implementation and verification DFT circuit ( MBIST/SCAN/BSCAN/IP-Test)
Define DFT SDC (timing constraint) strategy, collaborate with Backend Engineer to validate DFT circuit & sdc.
Tester pattern generation and silicon debug analysis/diagnosis
Work as project leader/Block coordinator. Control project schedule, support project members to ensure T/O on-time.
Qualifications
Familiar with Tessent/TMAX, Synthesis/Simulation/Formal Verification tools.
Excellent team and interpersonal skills
BS or MS degree in EE or CS related
Good English communication skills
Min 2 years working experience
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Date Posted: 14/04/2025
Job ID: 107726065