Synopsys is seeking for a Physical Design Engineer, plays a critical role in physical implementation of high speed IPs, testchip and subsystem, from RTL to GDS.
Responsibilities:
- Responsible for the physical implementation of high speed interface IPs, testchip and subsystem.
- Driving all aspects from RTL to GDS including timing and physical sign-off, in close interaction and collaborative team work with multiple functional groups (front end, analog, CAD) and the product team.
Requirements:
- Bachelor's Master's degree or above, major in Electrical, Electronic and Telecomunication Engineering, Computer Science, Automation and Control, Mechatronic Engineering or any other relevant
(Fresh graduates or those under 2 years of experience are also welcomed and offered on-the-job training to adapt to the position's requirements.)
- From 2 years of experience in physical design.
- Solid knowledge of the full VLSI design cycle from RTL to GDSII.
- Comprehensive understanding of the underlying concepts of IC design, implementation flows, physical and timing signoff.
- Proficient in software and scripting skills (Perl, Tcl, Python); knowledge of CAD automation methods.
- Familiar with place and route, synthesis, timing and power analysis tools ICC2, Design Compiler, PrimeTime, Redhawk.
Familiar with physical verification tools and flows ICV& Other PV tools for LVS, DRC, ERC, PERC.
- Strong desire to learn and explore new technologies.
- Demonstrates good analysis and problem-solving skills.
- Self-motivated, positive attitude, good communication skills and teamwork.
- Good English communication skills
Synopsys delivers leading silicon to systems design solutions that maximize our customers R&D capability and productivity. Companies trust Synopsys to pioneer new technologies getting them to market faster without compromise. 
