About the Role:
We are seeking a talented and experienced Physical Design Technical Lead to join our team and play a pivotal role in bringing our cutting-edge ASICs to life. You'll leverage your expertise in physical design and place & route to optimize performance, power, and area for complex system-on-chip (SoC) designs.
Responsibilities
- Participate in ASIC development project with emphasis in place and route implementation (block, subsystem and/or top-level), timing closure, low power, physical verification, power analysis and IR/EM with package.
- Coordinate and drive physical design activities of the SoC and support cross-functional engineering effort for signoff closure for tapeout.
- Work closely with frontend, integrating as well as DFT team to optimize performance, power and area.
- Participate in cutting-edge physical design methodology and flow development.
Requirements
- Must be a power user of Cadence suite (Innovus, QRC, Voltus) or Synopsys suite (ICC2, Fusion Compiler, StarRC, PTSI).
- Strong in ASIC physical design flow with low power, performance and area optimization techniques.
- Automation and programming-minded, solid coding experience in scripting languages.
- Knowledge of logic design principles, and DFT concepts.
- Successful track records of taping out SoCs in FinFet process is plus
- BS or MS degree in EE or CS related.
- Good English communication skills.
- At least 5 year working experience.
Benefits:
- Competitive salary and benefits package.
- Opportunity to work on cutting-edge projects and technologies.
- Collaborative and supportive work environment.
- Continuous learning and development opportunities.
- Career growth potential within a rapidly growing company.
Growth Opportunities:
- Candidates with 8 years or more experience will be considered for senior manager/technical lead positions.
- Candidates with less experience will be considered for junior positions with the opportunity to grow and learn.
. .
