Verilog Hdl Jobs

Staff Engineer, Physical Design

Permanent Job

Ho Chi Minh ,

Vietnam

5-7 years

EM/IR-Drop/Xtalk analysis primetime Fusion Compiler Verilog Hdl Synopsys suite Cadence suite chip synthesis PT-SI Physical Verification Innovus formal verification ASIC Celtic Timing Closure AstroRail IC Compiler PrimeRail static timing analysis Apache

24 days ago

Senior/Staff Design Verification Engineer

Permanent Job

Ho Chi Minh ,

Vietnam

2-4 years

industry-standard simulators verification methodologies debugging failures PCI-Express advanced verification techniques regression systems Uvm UCIe AMBA Asic Design Verification RTL designers revision control systems HBM CXL protocols C Hdl DDR Perl Verilog Ethernet System Verilog Python

4 days ago

SOC Engineering, Senior Engineer

Permanent Job

Ho Chi Minh ,

Vietnam

2-4 years

Uvm Hdl C Perl Verilog System Verilog Python

a month ago

Design Verification Senior / Staff Engineer

Permanent Job

Ho Chi Minh ,

Vietnam

5-7 years

Uvm Hdl C Perl Verilog System Verilog Python

a month ago

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Verilog Hdl Jobs

Staff Engineer, Physical Design

Senior/Staff Design Verification Engineer

SOC Engineering, Senior Engineer

Design Verification Senior / Staff Engineer